Lateral linear mode avalanche photodiode through 0.35 μm high voltage CMOS process
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1.Shanghai Institute of Technical Physics, Chinese Academy of Sciences, Shanghai 200083, China;2.University of Chinese Academy of Sciences, Beijing 100049, China;3.School of Information Science and Technology, ShanghaiTech University, Shanghai 201210, China;4.Nantong Academy of Intelligent Sensing, Nantong 226000, China

Clc Number:

TN364

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Supported by the Shanghai Pujiang Program (18PJ1410700), Key Laboratory of Defense Technology Funding of Chinese Academy of Sciences (CXJJ-20S004), and Innovation Program of Shanghai Institute of Technical Physics, Chinese Academy of Sciences (CX-268)

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    Abstract:

    This letter reports on a lateral linear mode avalanche photodiode through 0.35 μm high voltage CMOS process. The linear mode avalanche photodiode is designed and fabricated with the lateral separate absorption, charge and multiplication (SACM) structure using an epitaxial wafer. The DNTUB layer, DPTUB layer, Pi layer and SPTUB layer are used for the lateral SACM structure. This improves freedom of the design and fabrication for monolithic integrated avalanche photodiode without high voltage CMOS process modifications. The breakdown voltage for the lateral linear mode avalanche photodiode is about 114.7 V. The dark currents at gain M = 10 and M = 50 are about 15 nA and 66 nA, respectively. The effective responsive wavelength range is 450 ~ 1050 nm. And the peak responsive wavelength is about 775 nm at 20 V while M = 1. With unity gain (M = 1), the responsivity at 532 nm is about half of the maximum.

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JU Guo-Hao, CHENG Zheng-Xi, CHEN Yong-Ping. Lateral linear mode avalanche photodiode through 0.35 μm high voltage CMOS process[J]. Journal of Infrared and Millimeter Waves,2022,41(4):668~671

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History
  • Received:October 21,2021
  • Revised:August 15,2022
  • Adopted:November 24,2021
  • Online: August 10,2022
  • Published:
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