This paper presents a design method of high-power triple frequency multiplier based on on-chip integrated capacitor technology and band-stop filter structure. The DC bias circuits of the tripler was improved by using the on-chip integrated capacitor based on beam lead structure so that the DC feed and RF ground were achieved simultaneously. Also， a more compact structure of the tripler was built and the model accuracy was improved. Then， the bandstop filter was used to replace the traditional stepped impedance lowpass filter to suppress the third harmonic. Hence， the structure of the tripler is further simplified while the performance is improved. A 110 GHz tripler and a 220 GHz tripler were fabricated and measured， respectively. The results show that when the input power is 500 mW， the maximum output power of 110 GHz tripler reaches 140 mW with 30 % peak efficiency. When the input power is 300 mW， the peak efficiency of 220 GHz tripler reaches 15 % and the maximum output power is 45 mW. Performance of two triplers validates the design method.