Abstract
In this paper， a linear optimization method（LOM） for the design of terahertz circuits is presented， aimed at enhancing the simulation efficacy and reducing the time of the circuit design workflow. This method enables the rapid determination of optimal embedding impedance for diodes across a specific bandwidth to achieve maximum efficiency through harmonic balance simulations. By optimizing the linear matching circuit with the optimal embedding impedance， the method effectively segregates the simulation of the linear segments from the nonlinear segments in the frequency multiplier circuit， substantially improving the speed of simulations. The design of on-chip linear matching circuits adopts a modular circuit design strategy， incorporating fixed load resistors to simplify the matching challenge. Utilizing this approach， a 340 GHz frequency doubler was developed and measured. The results demonstrate that， across a bandwidth of 330 GHz to 342 GHz， the efficiency of the doubler remains above 10%， with an input power ranging from 98 mW to 141mW and an output power exceeding 13 mW. Notably， at an input power of 141 mW， a peak output power of 21.8 mW was achieved at 334 GHz， corresponding to an efficiency of 15.8%.
In recent decades， the demand for millimeter-wave and submillimeter-wave power sources has surged， driven by the expanding application of terahertz technology in fields such as remote sensing， high-speed communication， and radio astronom
As the mainstream technological solution for terahertz sources， research on Schottky diode frequency doublers has been increasing. The principle of frequency doubling with Schottky diodes primarily utilizes the diode's nonlinear characteristics， including varactor and varistor properties， to generate harmonic components at corresponding frequencies， which are then extracted and output through an E-plane waveguide probe structure. Varactor diodes excel in delivering higher power outputs with superior efficiency， whereas varistor diodes are distinguished by their ability to provide wider bandwidths. Balanced frequency doubler
The popular approach in terahertz circuit design combines three-dimensional electromagnetic field models with diode SPICE models through the coaxial probe method， enabling accurate prediction of the circuit performance. However， the specific implementation processes of different methods each have their own variations. The subdivision design method （SDM）
However， regardless of how 3D-EM is segmented into units in these mentioned design methods， the final simulation optimization still occurs within harmonic balance simulation software， thus the simulation speed is constrained by the speed of harmonic balance simulations. Recently， some efforts have been made to separate linear and nonlinear circuits
This paper introduces an impedance matching method that distinctly separates linear circuits from nonlinear circuits. The principal concept isolates the nonlinear circuit from the impedance matching process， connecting the two through the diode's harmonic embedding impedance in the linear circuit as determined by nonlinear simulations. This approach significantly improves simulation speed. To validate the accuracy and practicality of this design concept， a 340 GHz balanced frequency doubler circuit was designed and fabricated.
The balanced frequency doubler consists of a pair of in-phase， parallel-connected diodes mounted on the E-plane of the input waveguide， with the output signal transmitted to the output waveguide by means of an E-plane probe. Its unique topological structure allows the currents generated by odd harmonics to circulate between the diodes and the ground provided by the cavity， effectively making the entire diode unit act like a dipole antenna that excites TE modes in the waveguide. Meanwhile， the currents from even harmonics can generate TEM modes along the direction of the transmission line. This configuration results in mode isolation between the input fundamental signal and the output second harmonic signal， as well as impedance isolation. Consequently， input and output matching can be designed independently without concern for their coupling effects.
According to the principles， the design of a balanced frequency doubler circuit can be segmented into three parts： initially， individual harmonic balance simulations of the diodes are performed to determine their best operating harmonic embedding impedance； subsequently， the previously determined harmonic embedding impedance is utilized to design the input and output matching circuits separately； finally， the input and output matches are integrated into a complete circuit， and a comprehensive harmonic balance simulation is performed to predict the circuit's performance. The design process is illustrated in
Fig. 1 Linear optimization method design flow diagram （HB：Harmonic Balance）
图1 线性优化法的设计流程图
For frequency doublers based on Schottky diodes， the diode's parasitic and intrinsic parameters significantly impact the performance of the frequency doubler. To ensure the doubler operates optimally at 340 GHz， with the maximum output under a standardized 100 mW input， we optimized the intrinsic parameters of the diode based on measured data from a series of Schottky diodes with different diameters. The final intrinsic parameters of the diode are presented in
| Parameters | Value |
|---|---|
| Diameter， d | 5 µm |
| Reverse saturation current， Is | 22.8 fA |
| Zero bias junction capacitance， Cj0 | 21.6 fF |
| Ideal factor， η | 1.1 |
| Series resistance at DC measurement， Rs | 3.8 Ω |
| Reverse breakdown voltage， Vb | 12 V |
| Barrier voltage， Vj | 0.77 V |
| Grading coefficient， M | 0.418 |
Subsequently， harmonic balance simulations are performed on the diode model to extract both the fundamental and second harmonic embedding impedances， as depicted in the HB simulation section of
Fig. 2 Optimal input and output embedding impedances for the diode
图2 二极管的最佳输入输出嵌入阻抗
As mentioned in Section 2.1， the input fundamental signal operates in the TE10 mode， while the output second harmonic signal travels in the TEM mode. Their mode orthogonality ignores the need for an additional filter， reducing the complexity of the matching process. Moreover， the isolation between input and output impedances minimizes their mutual influence， allowing for the independent optimization of the input matching network.
As shown in
Fig. 3 Schematic of the waveguide cavity where the diode cell is suspended
图3 二极管单元悬置于波导腔体的示意图
Fig. 4 Schematic for optimization of the input matching network circuit
图4 输入匹配电路优化的原理图
Furthermore， the transmission structures in the output matching circuit might affect the field distribution of the TE10 mode， thereby influencing the transmission constants and characteristic impedance of the TE10 mode， as shown in
Fig. 5 Design of input matching network： （a） detailed dimensions of the input matching network； （b） comparison of PortZ0 and Epsilon for suspended and non-suspended microstrip lines with a width of 100 µm for the TE10 mode； （c） comparison of the diode's input embedding impedance with the impedance provided by the input matching network
图5 输入匹配网络的设计：（a）输入匹配网络的具体尺寸；（b）线宽100 µm的悬置微带与非悬置微带在TE10模下的PortZ0和等效介电常数的比较；（c）二极管的输入嵌入阻抗与输入匹配网络提供的阻抗之间的比较
Ultimately， the dimensions of the various parts of the input matching circuit obtained through simulations are shown in
The output matching circuit can be divided and designed in two parts： one from the diode to the suspended microstrip line in the channel， and the other encompassing the output probe transition， which includes a DC filter. These two parts are connected by introducing a fixed load impedance， ZL， in the middle to simplify the complexity of output matching. The load impedance is determined by the suspended microstrip line in the channel. Thus， when combining the two circuit parts， merely adjusting the length of the suspended microstrip line can minimize reflections between the two subcircuits. The specific principle is illustrated in
Fig. 6 Schematic for optimization of the output matching network circuit
图6 输入匹配电路优化的原理图
Fig. 7 Design of the output matching network： （a） detailed dimensions of the output waveguide matching； （b） the detail of the 340 GHz frequency doubler chip； （c） comparison of the diode's output embedding impedance with the impedance provided by the output matching network
图7 输出匹配电路的设计：（a）输入波导匹配的具体尺寸；（b）340 GHz二倍频芯片的具体细节；（c）二极管输出嵌入阻抗与输出匹配网络提供的阻抗之间的比较
Diverging from traditional high-low impedance filters， this design employs a CMRC （Compact Microstrip Resonant Cell） filter for the DC filtering section， aiming to minimize the overall length of the chip while ensuring robust RF suppression capabilities to ease assembly challenges. The resulting integrated output circuit's waveguide matching section is displayed in
After separately designing the input and output matching circuits， combining these two sections forms the complete frequency doubler circuit， which includes the monolithic circuit and the metal cavity. An E-plane split-waveguide block is produced through computer numerical control （CNC） milling technology and is further processed by electroplating. The diode chip is mounted on the split block and aligned through beam leads to ensure its correct placement. This step is critical， as the accuracy of alignment directly influences performance. Subsequently， the DC beam leads are connected to the chip capacitors and through capacitors to establish the DC pathway for the frequency doubler. Lacking thermo-compression bonding facilities， conductive adhesive is used to attach the beam leads to the cavity. However， this approach does not offer sufficient strength， making the chip prone to shifting during the disassembly of the cavity. This may also explain the significant discrepancies between our empirical results and the simulations. The fully assembled frequency doubler is illustrated in
Fig. 8 Assembled frequency doubler
图8 装配好的二倍频器
The constructed test system is shown in
Fig. 9 Diagram of the frequency doubler test setup
图9 二倍频器测试系统原理图
Fig. 10 Test results of the 340 GHz doubler： （a） measured input power and output power versus frequencies； （b） comparison of measured efficiency and simulated efficiency with different series resistances （simulated input power Pin=150 mW）
图10 340 GHz二倍频器的测试结果：（a）测量的输入功率和输出功率随频率的变化； （b）不同串联电阻下测量效率与仿真效率之间的比较 （仿真输入功率Pin=150 mW）
As shown in
Fig. 11 The effect of assembly errors on output： （a） schematic of the lateral assembly error； （b） impact of different offset values on the output efficiency， with Rs•Cj0 = 120 Ω•fF and Pin=150 mW
图11 装配误差对输出造成的影响： （a）横向装配误差示意图；（b）不同的偏移值对输出效率的影响，Rs•Cj0 = 120 Ω•fF and Pin=150 mW
Fig. 12 Defects on the surface of the output waveguide
图12 输出波导表面的缺陷
| Ref. | Output Frequency （GHz） | Pin（mW） | Peak Pout（mW） | Design Method |
|---|---|---|---|---|
|
［ | 177-202 | 50-95 | 13 | SDM |
|
［ | 200-240 | 20-120 | 5 | SDM |
|
［ | 135-190 | 30-174 | 17.8 | GDM |
|
［ | 210-234 | 42-97 | 16 | FHIMO |
|
［ | 205-225 | 10-50 | 13 | FMWW |
|
［ | 135-150 | 10-70 | 3.5 | Quality factors scaling |
| This work | 322-342 | 35-146 | 21.8 | LOM |
In this paper， a strategy to boost the design efficiency of terahertz frequency multipliers is proposed. This method separates the circuit into linear and nonlinear parts for distinct simulations. By using the diode's nonlinear properties in the linear circuit's embedding impedance， it connects the two parts. This separation of harmonic balance from S-parameter simulations helps to reduce simulation time. Following this strategic framework， a 340 GHz frequency doubler was developed and subjected to empirical validation. Performance evaluations revealed that within a bandwidth of 330 GHz to 342 GHz， the efficiency of the device consistently surpasses 10%， with the input power oscillating between 98 mW and 141 mW， and the output power starting from 13 mW. Remarkably， with an input power set at 141 mW， the device achieved a peak output of 21.8 mW at 334 GHz， translating to an efficiency rate of 15.8%. The practical application of this frequency doubler effectively demonstrates the viability of the suggested approach. This technique promises adaptability for a wide range of applications in terahertz circuits， particularly for complex harmonic structures like mixers and compact modules.
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