Aiming at the problem that the calculation quantity and accuracy are incompatible during the thermal stress simulation analysis of large area array mercury cadmium telluride chips, an optimization simulation model for coupled thermal stress is established by introducing small-scale indium column arrays at different positions in the interconnection area of the chip. Thermal stress analysis using this model shows that significant thermal stress is generated near the upper and lower surfaces of the indium column, while greater thermal stress is generated inside the array element at the edges and corners, up to 225.69 MPa. Furthermore, the structure of the chip is optimized to obtain the optimal readout circuit and zinc-cadmium tellurium substrate thickness. In addition, the simulation results show that single-sided indium is an indium column structure with low thermal stress, and reducing the radius of the indium column can further reduce its internal thermal stress. The proposed thermal stress simulation optimization model provides a more accurate and effective analysis method and device design′s theoretical guidance for the thermal stress analysis of large area array mercury cadmium telluride chips.