In the fabrication process of GaAs integrated passive device (IPD), via-hole etching is an important link. GaAs at the edges of the etched holes is etched, which can cause chipping and adversely affect device performance and reliability. In this paper, the thickness of GaAs for via-hole etching is not less than 200 μm, and the edges of the via-holes are not etched to achieve smooth connection of metal wires. The photoresist and metal are used as a mask to effectively solve the problem that the single photoresist is deformed due to excessive thickness or a thin thickness causes the GaAs substrate to be etched. By optimizing the process, under the conditions of a photoresist thickness of 32 μm, a metal mask thickness of 0.5 μm, a metal etching time of 60 s and an inductively coupled plasma (ICP) etching of 4000 s, the morphology of a hole depth of 200 μm and a flat via-hole edge are obtained. The main reason and mechanism of GaAs chipping are analyzed, and the chipping problem of 200 μm via-holes is solved by the optimized process, thereby improving the device performance and reliability.