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GaAs基通孔刻蚀的崩边形成机理研究
投稿时间:2019-10-21  修订日期:2019-10-22  点此下载全文
引用本文:黄光伟,马跃辉,李立中,林伟铭,吴淑芳,陈智广,林豪,庄永淳,吴靖.GaAs基通孔刻蚀的崩边形成机理研究[J].红外,2019,40(10):26~31
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作者单位E-mail
黄光伟 福建省福联集成电路有限公司 guangwei_huang@unicompound.com 
马跃辉 福建省福联集成电路有限公司  
李立中 福建省福联集成电路有限公司  
林伟铭 福建省福联集成电路有限公司  
吴淑芳 福建省福联集成电路有限公司  
陈智广 福建省福联集成电路有限公司  
林豪 福建省福联集成电路有限公司  
庄永淳 福建省福联集成电路有限公司  
吴靖 福建省福联集成电路有限公司  
中文摘要:在砷化镓(GaAs)集成无源器件(Integrated Passive Device, IPD)的制作工艺中,通孔刻蚀是一道重要环节。蚀刻孔边缘的GaAs会被蚀刻,由此引发崩边并对器件性能及可靠性造成不利影响。本文中,用于通孔蚀刻的GaAs厚度不小于200 μm,通孔边缘没有被蚀刻的痕迹,以实现金属导线的平滑连接。采用光阻和金属来充当掩膜,有效解决了单一光阻因厚度过高而变形或者厚度薄导致GaAs衬底被蚀刻的问题。通过优化工艺,在光阻厚度为32 μm、金属掩膜厚度为0.5 μm、金属蚀刻时间为60 s以及感应耦合等离子体(Inductively Couple Plasma, ICP)蚀刻4000 s的条件下,得到了孔深为200 μm且通孔边缘平整的形貌。分析了 GaAs 崩边形成的主要原因与机理,并通过优化工艺解决了200 μm通孔的崩边问题,从而提高了器件性能及可靠性。
中文关键词:集成无源器件  砷化镓  深背部通孔  崩边
 
Study on Formation Mechanism of Chipping in GaAs-based Via-hole Etching
Abstract:In the fabrication process of GaAs integrated passive device (IPD), via-hole etching is an important link. GaAs at the edges of the etched holes is etched, which can cause chipping and adversely affect device performance and reliability. In this paper, the thickness of GaAs for via-hole etching is not less than 200 μm, and the edges of the via-holes are not etched to achieve smooth connection of metal wires. The photoresist and metal are used as a mask to effectively solve the problem that the single photoresist is deformed due to excessive thickness or a thin thickness causes the GaAs substrate to be etched. By optimizing the process, under the conditions of a photoresist thickness of 32 μm, a metal mask thickness of 0.5 μm, a metal etching time of 60 s and an inductively coupled plasma (ICP) etching of 4000 s, the morphology of a hole depth of 200 μm and a flat via-hole edge are obtained. The main reason and mechanism of GaAs chipping are analyzed, and the chipping problem of 200 μm via-holes is solved by the optimized process, thereby improving the device performance and reliability.
keywords:lintegrated passive device  GaAs  deep backside vias  chipping
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