To address the requirements for ultra-low noise and zero-bias operation in MoS?-BP-MoS? van der Waals photovoltaic detectors， a readout circuit was designed based on a capacitive transimpedance amplifier （CTIA） incorporating chopper stabilization （CS） and correlated double sampling （CDS） techniques. The design employed a multi-node chopper architecture operating at 40 kHz to suppress 1/f noise， while CDS was utilized to eliminate KTC noise and ripple. A unity-gain buffer provided dynamic bias control， achieving a bias error below 200 μV. Experimental results demonstrated an equivalent input noise current of 119.35 fA， a total integrated noise reduction of 32.83%， and a power consumption of 990 μW in a 0.35 μm CMOS process. This work presents a high-precision， low-noise readout solution for two-dimensional material photodetectors.