基于双CTIA的热释电红外探测器读出电路设计
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作者单位:

1国科大杭州高等研究院,浙江 杭州 310024;2中国科学院大学,北京 100049;3复旦大学 集成芯片与系统全国重点实验室 集成电路与微纳电子创新学院,上海 200043;4中国科学院上海技术物理研究所 红外科学与技术全国重点实验室,上海 200083;5复旦大学 光电研究院,上海 200433

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TN402;TN215

基金项目:

国家自然科学基金62025405 (J.W.)、国家重点研发计划2021YFA1200700 (J.W.)、浙江省自然科学基金No.LD25F040001


Design of readout circuit for pyroelectric infrared detectors based on dual-CTIA structure
Author:
Affiliation:

1Hangzhou Institute for Advanced Study, University of Chinese Academy of Sciences, Hangzhou 310024, China;2University of Chinese Academy of Sciences, Beijing 100049, China;3State Key Laboratory of Integrated Chips and Systems, College of Integrated Circuits and Micro-Nano Electronics, Fudan University, Shanghai 200433, China;4State Key Laboratory of Infrared Physics, Shanghai Institute of Technical Physics, Chinese Academy of Sciences, 500 Yu Tian Road, Shanghai 200083, China;5Institute of Optoelectronics, Shanghai Frontier Base of Intelligent Optoelectronics and Perception, Fudan University, Shanghai 200433, China

Fund Project:

Supported by the National Natural Science Foundation of China (62025405); National key research and development program in the 14th five year plan (2021YFA1200700); Zhejiang Provincial Natural Science Foundation of China (LD25F040001).

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    摘要:

    为了实现对热释电红外探测器极弱信号的检测和高灵敏度应用场景中的需求,提出了一种具有可变阵列规模的双电容跨阻放大器(CTIA)读出结构,并设计了带隙基准(Bandgap)、低压差线性稳压源(LDO)作为偏置电路提供电压偏置,以满足低噪声、低功耗、大动态范围和便携式的需求。采用TSMC 0.18 μm 1P6M工艺设计电路,电源电压为3.3V,并对其版图进行绘制,采用伪晶体管(Dummy)结构、保护环(Guard Ring)结构,以提升器件之间的匹配度和版图整体的对称性以及模拟电路的抗干扰能力与电气稳定性。

    Abstract:

    To achieve the detection of extremely weak signals from pyroelectric infrared detectors and to meet the demands of high-sensitivity applications, this paper proposes a dual-capacitor transimpedance amplifier (CTIA) readout structure featuring a variable array size. Additionally, a bandgap reference and a low dropout regulator (LDO) are designed as the bias circuit to provide voltage bias, in order to meet the requirements of low noise, low power consumption, large dynamic range and portability. The circuit is designed in TSMC 0.18μm 1P6M CMOS process under a 3.3V supply. For the layout implementation, advanced techniques, including dummy structures and guard rings, are employed to improve device matching, overall layout symmetry, as well as the noise immunity and electrical stability of the analog circuitry.

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  • 收稿日期:2025-12-08
  • 最后修改日期:2026-03-05
  • 录用日期:2026-01-12
  • 在线发布日期: 2026-03-01
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