Cavity-backed On-chip Patch Antenna in 0.13-μm SiGe BiCMOS Technology
Received:August 02, 2018  Revised:August 02, 2018  download
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Author NameAffiliationE-mail
Xiao Jun School of Electronic Engineering,University of Posts and Telecommunications,Beijing,China xiaojun19861986@163.com 
Li Xiu-Ping School of Electronic Engineering,University of Posts and Telecommunications,Beijing,China xpli@bupt.edu.cn 
Qi Zi-Hang School of Electronic Engineering,University of Posts and Telecommunications,Beijing,China  
Zhu Hua School of Electronic Engineering,University of Posts and Telecommunications,Beijing,China  
Feng Wei-Wei School of Electronic Engineering,University of Posts and Telecommunications,Beijing,China  
Abstract:This letter presents a 340-GHz cavity-backed on-chip patch antenna design and fabrication using standard 0.13-μm SiGe BiCMOS technology. The patch placed at AM layer is fed by a stripline at LY layer through via holes from LY to AM layer. The via holes are built between the top metal layer (AM layer) and the ground plane (M1 layer) to form a cavity which improves the impedance matching bandwidth and the radiation performances of the antenna. The proposed antenna shows a simulated impedance bandwidth of 9.2 GHz from 335.6 to 344.8 GHz for S11 less than -10 dB. The simulated gain of the antenna at 340 GHz is 3.2 dBi. The total area of the antenna is 0.5×0.56 mm2.
keywords:0.13-μm SiGe BiCMOS technology, cavity backed, patch antenna, on-chip antenna.
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Copyright:《Journal of Infrared And Millimeter Waves》