基于平面肖特基二极管的75~110 GHz宽带三倍频器芯片
作者:
作者单位:

1.中国电子科技集团公司 第十三研究所,石家庄 050051;2.南通大学 微电子学院(集成电路学院),南通 226019;3.华东师范大学 物理与电子科学学院,上海 200241

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中图分类号:

TN315.3

基金项目:

国家自然科学基金重点项目(62034003)


75~110 GHz wideband frequency tripler chip based on planar schottky diode
Author:
Affiliation:

1.The 13th Research Institute, China Electronics Technology Group Corporation, Shijiazhuang 050051, China;2.School of Microelectronics (School of Integrated Circuits), Nantong University, Nantong, 226019, China;3.School of Physics and Electronic Science, East China Normal University, Shanghai, 200241

Fund Project:

Supported by the National Natural Science Foundation of China (62034003)

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    摘要:

    基于GaAs平面肖特基二极管工艺,采用反向并联二极管对的平衡结构,实现了W波段宽带三倍频器芯片。采用有限元法和等效电路法联合的方式,建立10~280 GHz频率范围的平面肖特基二极管的精确等效电路模型。采用非线性谐波平衡联合仿真方法,实现了W波段倍频器的最优化设计。在片测试结果表明,在17 dBm的驱动功率下,倍频损耗小于15 dB,最大倍频效率6.7%,芯片尺寸0.80 mm×0.65 mm ×0.05 mm。

    Abstract:

    Based on the GaAs planar Schottky diode process, a W band wideband frequency tripler MMIC is designed with a reverse parallel diode pair. By combining the finite element method and equivalent circuit method, an accurate equivalent circuit model of the planar Schottky diode is built in the frequency range of 10~280 GHz. The nonlinear harmonic balance tool is utilized to achieve the optimal frequency tripler design in the W band. The measurement results show that the frequency multiplication loss is less than 15 dB under 17 dBm driving power, and efficiency up to 6.7%. The chip size is 0.80 mm×0.65 mm×0.05 mm.

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引用本文

陈艳,孟范忠,薛昊东,张傲,高建军.基于平面肖特基二极管的75~110 GHz宽带三倍频器芯片[J].红外与毫米波学报,2024,43(6):768~774]. CHEN Yan, MENG Fan-Zhong, XUE Hao-Dong, ZHANG Ao, GAO Jianjun.75~110 GHz wideband frequency tripler chip based on planar schottky diode[J]. J. Infrared Millim. Waves,2024,43(6):768~774.]

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  • 收稿日期:2024-03-03
  • 最后修改日期:2024-11-06
  • 录用日期:2024-04-17
  • 在线发布日期: 2024-11-06
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