A 10-bit ramp generator for column-level Analog-to-Digital Converter (ADC) circuits of CMOS image sensors is designed. The integral structure, operation mode and simulation result of the circuit is presented in detail. In the circuit, a two-stage conversion mode is used and a resistor-array ramp generator is designed. The circuit design, simulation and layout design are achieved on the platform of Cadence. The proposed ramp generator is taped out in an 0.5 μm DPTM CMOS process. The simulation result shows that this design meets the related requirements basically.